1. Field of the Invention
The present invention relates to a device for reading cells of a memory device, particularly a multi-level state cell memory device.
2. Discussion of the Related Art
Multi-level state cell memory devices are devices in which each multi-level state cell stores multiple information bits. To enable a multi-level state cell to store multiple information bits, each multi-level state cell must be capable of storing two logic (voltage) levels for each bit stored. For example, in order that each cell may store two information bits, it is necessary to have four possible charge levels on the floating gate. To read a multi-level state cell, it is necessary to have three references to discriminate between the four possible voltage levels and provide the corresponding binary information encoded in the two bits of the multi-level state cell. In addition, the reading device must include a "multi-level state" reading amplifier.
An example of a memory structure using multi-level state cells is given in the U.S. Pat. No. 5,438,546. In this structure, each of the multi-level state read amplifiers receives three voltage references to make the necessary comparisons and provide information encoded in two bits of the multi-level state cell. In this example, the read amplifier used is of the same type as those used for a normal memory cell having only one encoded bit.
However, for multi-level state cells, it should be possible to determine the voltage level actually memorized in the cell without any ambiguity. Thus, the voltage levels must be sufficiently separated for bit information to be read reliably, without possible confusion between any two voltage levels. It is therefore necessary to have a forbidden zone around each current reference wherein current should not be present. This forbidden zone is shown in FIG. 1 as I.sub.F. FIG. 1 represents the distribution of read current for a multi-level state cell memory.
Each voltage level corresponds to a reference interval. In the figure, there are three reference currents: I.sub.ref1, I.sub.ref2, I.sub.ref3 defining four permitted zones corresponding to the binary values 00, 01, 10 and 11. The forbidden zone around each current reference may be obtained in various ways. Consider the example of programming cells by hot electrons (the case of EPROM cells). An unprogrammed cell has a low threshold voltage (and therefore high read current). To program the cell, it is necessary to apply a first high-voltage programming pulse to the cell and then to perform a verification read operation and then a programming pulse is reapplied, etc., until an interval is found corresponding to the information to be programmed. To be certain that the cell will be programmed at the correct voltage level while not infringing the forbidden zone area, there is provision for the methodical subtraction from, or addition to the cell current, of a demarcation current I.sub.margin, during the verification read operation. For example, to program the binary word 01, a check will be made to determine if Icell-Imargin &gt;I.sub.ref0. When the inequality is verified, the programming is terminated. In this way, it is certain that even if the programmed cell thereafter loses a little charge or even if, on the contrary, its charges increase slightly, an accurate reading will be done all the same.
To read the binary word memorized in a selected cell, the read current of this cell must be compared with each of the three current references. Then an encoding circuit delivers the corresponding binary word. A read of the cell can be performed by typical read comparators with current-voltage converters and voltage comparison. However, in this case, a different voltage reference is required for each comparator, requiring a total of three associated voltage reference circuits. Furthermore, these read comparators are fairly complicated to enable reliable and high-speed discrimination with respect to a given voltage reference. In addition, these read comparators consume a great deal of power and take up a large amount of space.
Therefore, what is needed is an approach that is more compact and consumes less power than current solutions. In particular, a solution which does not require voltage references circuits is desired.